The company is looking to enhance logic/RTL design for IPs and SoCs by conceptualizing, documenting, and designing Tools, Flows, and Methods (TFM) to improve design efficiency, quality, and integration across architectures and process nodes, ultimately optimizing power, performance, and area (PPA) and enabling faster convergence and seamless integration.
Requirements
- 8+ years of experience in semiconductor design in areas such as RTL simulation, design verification and/or synthesis.
- Proficiency in Python for software development.
- Familiarity with EDA data formats such as Liberty, SDC, SDF, VCD/FSDB.
- Experience working with Git in large collaborative development environments.
- Familiarity with industry-standard EDA tools and front-end design flows (RTL, simulation, verification, linting, synthesis).
- Advanced proficiency in Python, with strong object-oriented design skills.
- Proficiency in Docker and Kubernetes for containerized EDA workflows.
Responsibilities
- Design and develop TFM solutions for logic/RTL design and IP/SoC integration.
- Define and implement methodologies that optimize PPA on advanced architectures and process nodes.
- Analyze retrospective data to identify gaps and propose incremental or transformative improvements.
- Collaborate with logic design teams to enhance RTL design flows and convergence strategies.
- Develop automation and infrastructure to support RTL development, simulation, and physical design.
Other
- BS/MS in Computer Science, Electrical Engineering, or related field with 10+ years of experience.
- Excellent debugging and problem-solving skills with a focus on software robustness and maintainability.
- Knowledge of build systems (e.g., Make, CMake, Gradle) and dependency management.
- Experience with cloud-based or hybrid on-prem/cloud development environments.
- Ability to thrive in a fast-paced, collaborative environment.
