Meta Reality Labs Silicon is looking for an AR Subsystem Performance Architect to analyze key workloads and architect subsystems that are SW usable, performant, and power efficient.
Requirements
2+ years of performance modeling experience with programming (C/C++ or SystemC-TLM) and scripting (Python)
1+ years of experience evaluating architectural trade-offs in performance key performance metrics
1+ years of expertise with post-silicon to pre-silicon correlation analysis
1+ years of experience with System on Chip (SoC) Architecture, NoCs, memory subsystems, and heterogeneous compute principles
2+ years of experience with bare-metal programming, micro-benchmarking, etc
Exposure to power concepts and low power design principles
Familiarity with developing and utilizing telemetry solutions to analyze and profile workloads
Responsibilities
Own performance models for system interconnect, cache, memory hierarchy analysis
Own Subsystem Network on Chip (NoC) architecture specification, design and characterization
Lead Intellectual Property (IP) performance bottleneck analysis using traffic traces from pre/post silicon platforms
Lead analysis and configuration of subsystem caches for optimal performance
Drive IP latency hiding features and Quality of Service (QoS) recommendations for each compute engine
Collaborate with various partners to deliver documentation and proof of concepts for workloads running on these subsystems
Other
Currently has, or is in the process of obtaining a Bachelor's degree in Computer Science, Computer Engineering, relevant technical field, or equivalent practical experience. Degree must be completed prior to joining Meta
Act as a key point-of-contact representing the team with varying internal and external partners, in a highly cross-functional environment
