ByteDance is looking to build industry-leading, highly efficient, and scalable video codec hardware solutions (FPGA and ASIC) from the ground up to better serve its billions of users.
Requirements
- Knowledge of Video Codecs
- Experience with RTL design (SystemVerilog) or High level Synthesis (HLS)
- Experience with UVM methodology, SystemC, or DPI
- Good programming skills in Python for task automation
- Currently pursuing a PhD in computer science/electrical engineering or a related technical discipline
Responsibilities
- Apply your knowledge of computer architecture and ASIC design to create ASIC design for compressing, processing still images and videos.
- As a Design Verification engineer, you will be taking on an important role in helping deliver a Video Codec IP by generating test benches and running simulations.
- Interface with architects and ASIC/FPGA design engineers to develop test plans, lead bug tracking, and automation of regression testing.
- Design hardware accelerators for advanced video encoding and processing.
- Work closely with architecture, algorithm and verification team to build high performance and low power video processing IPs.
- Utilize knowledge in real-world scenarios while laying a strong foundation for personal and professional growth.
- Contribute to the development of fundamental skills and explore potential career paths.
Other
- Currently pursuing a PhD in computer science/electrical engineering or a related technical discipline
- Please state your availability clearly in your resume (Start date, End date)
- 10 paid holidays per year and paid sick time (56 hours if hired in first half of year, 40 if hired in second half of year)
- Day one access to health insurance, life insurance, wellbeing benefits and more
- Interns who are not working 100% remote may also be eligible for housing allowance
