Meta is looking to build cutting edge ASICs in fields such as machine learning, video transcoding and network acceleration.
Requirements
- 8+ years of experience in micro-architecture and RTL development for complex control and data path IPs OR Experience in SoC Micro-architecture, Design and Integration
- RTL development using Verilog, System Verilog and HLS
- Experience in CPU, NOC, Memory and Peripheral Subsystems
- Experience with Synthesis, Timing Closure and Formal Verification Methodology
- Experience in data path development
Responsibilities
- Architecture exploration
- Micro-architecture development
- Soft and hard IP identification, selection and integration. Collaboration with verification and emulation teams in test plan development and debug
- Collaboration with implementation team to close the design on timing and power
Other
- Bachelor's degree in Computer Science, Computer Engineering, relevant technical field, or equivalent practical experience
- Master’s or PhD degree in Electrical Engineering, Computer Science or related areas
- Meta is proud to be an Equal Employment Opportunity and Affirmative Action employer.
- Meta is committed to providing reasonable accommodations for candidates with disabilities in our recruiting process.
