Filtr uses AI to scan 1000+ jobs and finds postings that perfectly matches your resume

Meta is looking for individuals with experience in Design Verification to build IP and System On Chip (SoC) for data center applications.

Requirements

• 3+ years of hands-on experience in SystemVerilog/UVM methodology or C/C++ based verification
• 3+ years experience in block/IP/sub-system and/or SoC level verification based on SystemVerilog UVM/OVM based methodologies
• Experience in EDA tools and scripting (Python, TCL, Perl, Shell) used to build tools and flows for verification environments
• Experience in architecting and implementing Design Verification infrastructure and executing the full verification cycle
• Experience in development of Universal Verification Methodology (UVM) based verification environments from scratch
• Experience with verification of Advanced RISC Machines/Reduced Instruction Set Computing Five (ARM/RISC-V) based sub-systems or System-on-Chip (SoCs)
• Experience with IP or integration verification of high-speed interfaces like Peripheral Component Interconnect Express (PCIe), Double Data Rate (DDR), Ethernet

Responsibilities

• Define and implement block/IP/System on Chip (SoC) verification plans, build verification test benches to enable block/IP/sub-system/SoC level verification
• Develop functional tests based on verification test plan
• Drive Design Verification to closure based on defined verification metrics on test plan, functional and code coverage
• Debug, root-cause and resolve functional failures in the design, partnering with the Design team
• Collaborate with cross-functional teams like Design, Model, Emulation and Silicon validation teams towards ensuring the highest design quality

Other

• Currently has, or is in the process of obtaining a Bachelor's degree in Computer Science, Computer Engineering, relevant technical field, or equivalent practical experience.
• Degree must be completed prior to joining Meta
• Track record of 'first-pass success' in Application-Specific Integrated Circuit (ASIC) development cycles
• Experience with revision control systems like Mercurial(Hg), Git or SVN