Berkeley Lab's Applied math and Computational Sciences Division is looking to evaluate and develop devices to hardware/circuit co-design flow for architectural specializations for high performance computing neuromorphic and edge computing applications in the absence of Moore's Law Scaling.
Requirements
- PhD or equivalent in a Computing Science or Computer Engineering-related scientific discipline
- Past Experience in either Machine learning accelerators or SRAM array design or basic blocks of processor at transistor level and/or Superconducting circuit design.
- Courses or experience in CAD for VLSI algorithms and C++ Programming.
- Proficient in Spice Circuit Simulations, Verilog and hardware design in CMOS, FeFET, NCFET etc.
- Familiarity with hardware EDA/CAD tools and evaluation/modelling tools in order to extend existing infrastructure to rapidly evaluate CMOS designs.
- Experience with the use of script languages and system utilities such as configure, Perl, UNIX shell scripts, and 'make.'
- Experience with coding in C++/python for CAD tool development for ASIC design.
Responsibilities
- Design circuits, hardware accelerators and processor architectures using post-Moore devices to accelerate key HPC applications and application kernels.
- Develop compact models and methodologies to use these circuits for performance and energy characterizations which can be used in architectural simulation framework for tightly integrating these accelerators into heterogeneous systems and SoCs that may contain multiple different kinds of accelerator devices.
- Identify opportunities and challenges for devices to architectural design space exploration for several post-Moore devices to address those bottlenecks and develop circuit design models to determine the performance potential for those solutions.
- Develop architectural and circuit models for emulation in FPGA hardware
- Develop metrics and benchmark tests in order to compare conventional CMOS based processors/accelerators and enhanced post-Moore devices based computational accelerators for key HPC applications and algorithms.
- Publish work in academic journals and present it at conferences and workshops.
- Lead and assist in the preparation of proposals for funding.
Other
- Mandatory 3 Years of Postdoctoral research experience or equivalent research experience.
- Demonstrated creativity, initiative and ability to design, develop and implement complex solutions in consultation with designated technical expert(s) and/or supervisor.
- Experience and track-record writing technical papers and reports.
- Proven record of working effectively in a team, seeing projects through to completion, meeting deadlines, interacting with users, and thorough documentation of contributions.
- Willingness to learn and develop skills in new topics.
