SK hynix Memory Solution is seeking an intern to contribute to ongoing ASIC projects, requiring design database management, RTL logic coding, simulation execution and debugging, and cross-functional communication.
Requirements
- Must have proficiency in Verilog, SystemVerilog programming language
- Scripting language skills such as Python, Perl, Tcl, etc.
- Understand ASIC/FPGA workflow from concept to real silicon
Responsibilities
- Perform design database management; proper check-in’s of golden files, reverting unused changes, merge different files
- Should be able to code RTL logic with Verfilog syntax
- Should be able to run simulation using Synopsys VCS
- Should be able to debug simulation environment; compilation failure, simulation hang, simulation functional failure, etc
- Should be able to communicate with designers, verification engineers, and other team for the correct solution
Other
- Must have background in electronics, electrical engineering, computer science
- Must have good communication within co-working environments
- Must have good work ethic, i.e. punctual on deadline, trustworthy commitment on assignment.
- Have a mindset on problem solving
