Marvell is looking to develop high core-count AI compute platforms, 5G and 6G acceleration silicon, and custom ASIC designs for industry leading customers, and needs an intern to work on design verification and DFT/DV tasks
Requirements
- VLSI/SCAN/ATPG and UVM/Verification coursework preferred
- Desire to work with scan/ATPG, memory BIST, using Siemens tools
- Desire to work with System Verilog, UVM, Verification Test Plans, Coverage Driven Verification, Code Coverage, verification environments, test case simulation and debug
- Working towards a Bachelor’s degree in Computer Science, Electrical Engineering or related fields
- Experience with UVM based verification
- Experience with Siemens EDA tool
- Knowledge of JTAG, 1687, and chiplet to chiplet test busses
Responsibilities
- UVM test case development when new DFT RTL is added into a design
- Opportunities for script development where technical details of the underlying DFT architecture are abstracted into control files
- Opportunity to work with JTAG, 1687, end evolving chiplet to chiplet test busses
- Use of 1687 ICL/PDL to automate the creation of functional test patterns deployed on ATE
- Debug of high speed IOs to include DDR and SERDES, collaborating with designers, internal and third-party IP developers
- Use of Siemens EDA tools to insert scan and memory BIST, and the verification of these inserted test elements
- Opportunities in ATE pattern development
Other
- Working towards a Bachelor’s degree in Computer Science, Electrical Engineering or related fields
- Desire to work with scan/ATPG, memory BIST, using Siemens tools
- Medical, dental and vision coverage, perks and discount programs, wellness & mental health support including coaching and therapy
- Paid holidays, paid volunteer days and paid sick time
- Additional compensation may be available for intern PhD candidates
