Meta's Reality Labs (RL) is looking to deliver Meta's vision through Augmented Reality (AR) by developing custom silicon to meet the compute power requirements of AR, which requires breakthrough work in computer vision, machine learning, mixed reality, graphics, displays, sensors, and new ways to map the human body.
Requirements
- 2+ years ASIC development cycle industry experience
- 2+ years of hands-on experience in Verilog, SystemVerilog, C/C++ based verification and UVM methodology
- 2+ years experience in IP/sub-system and/or SoC level verification based on SystemVerilog UVM/OVM based methodologies
- Experience in one or more of the following areas along with functional verification - SV Assertions, Formal, Emulation
- Experience in EDA tools and scripting (Python, TCL, Perl, Shell) used to build tools and flows for verification environments
- Experience in architecting and implementing Design Verification infrastructure and executing the full verification cycle
Responsibilities
- Work with researchers and architects defining verification plans for each of the different core IP
- Define and track detailed test plans for the different modules and top levels
- Drive Design Verification to closure based on defined verification metrics on test plan, functional and code coverage
- Debug, root-cause and resolve functional failures in the design, partnering with the Design team
- Collaborate with cross-functional teams like Design, Model, Emulation and Silicon validation teams towards ensuring the highest design quality
- Develop and drive continuous Design Verification improvements using the latest verification methodologies, tools and technologies from the industry
Other
- Currently has, or is in the process of obtaining a Bachelor's degree in Computer Science, Computer Engineering, relevant technical field, or equivalent practical experience
- 2+ years of experience in the industry
- Must be able to work in California if hired for this position
- Must be willing to work with cross-functional teams
- Must have excellent communication skills
