Texas Instruments is looking to shape the future of electronics by hiring Design Verification interns to ensure pre-silicon verification success for their semiconductor products.
Requirements
- SystemVerilog functional coverage models of mixed-signal circuits for voltages and currents, real numbers, integers, and traditional digital functional coverage.
- RTL and Gates+SDF
- Constrained-random stimulus and auto-checking verification environments, especially constrained-random analog stimulus.
Responsibilities
- Developing detailed verification plans while working closely with the design and system team to ensure pre- silicon verification success
- Developing test benches, tests and simulations to DUT behavior
- Running coverage regressions to meet the defined coverage goals for SystemVerilog functional coverage models of mixed-signal circuits for voltages and currents, real numbers, integers, and traditional digital functional coverage.
- Work with regression tools and develop scripts to submit cases for regression analysis
- Utilize RTL and Gates+SDF, including verifying chip-level timing between analog and digital circuits.
- Constrained-random stimulus and auto-checking verification environments, especially constrained-random analog stimulus.
- Contribute to continuous improvements for quality and efficiency on DV strategy, tools, methods and flows
Other
- Currently pursuing an undergraduate or graduate degree in Electrical Engineering, Computer Engineering or Electrical & Computer Engineering
- Cumulative 3.0/4.0 GPA or higher
- Ability to establish strong relationships with key stakeholders critical to success, both internally and externally
- Strong verbal and written communication skills
- Ability to quickly ramp on new systems and processes
