Cadence plays a critical role in creating the technologies that modern life depends on. We are a global electronic design automation company, providing software, hardware, and intellectual property to design advanced semiconductor chips that enable our customers create revolutionary products and experiences.
Responsibilities
- Understand Design specification and develop test/coverage plan.
- Development of constrained random verification environments and verification components.
- Writing tests/sequences/functional coverage/assertions to meet verification goals.
Requirements
- Understanding of SV/UVM.
- Good knowledge of Verilog/Vhdl/C/C++
- Experience in any scripting language Perl/Python/Shell.
- Good debugging skills.
- Familiarity with ARM/CPU architectures.
- Good knowledge of some of the protocols like UART, I2C, SPI, JTAG
- Knowledge of AMBA protocols. (AXI/AHB/APB).
- Hands on experience in writing tests/sequences/functional coverage.
- Prior experience with Cadence verification tools and flows is highly desirable.
Other
- Strong vocabulary, communication, planning, and presentation skills are essential.
- Ability to work with high quality output and results in a fast paced and dynamic environment.
- Ability and desire to learn new methodologies, languages, protocols etc.
- Must be open to constant personal development and growth to meet the evolving demands of the semiconductor industry.
- Self-motivated and willing to take up additional responsibilities to contribute to team’s success.