Rambus is seeking to hire an exceptional Senior/Principal Design Verification Engineer to join their Memory Controller IP team to participate in pre-silicon RTL Verification activities related to Memory Controller SoftIP development, on leading-edge DDR, HBM, and GDDR DRAM controller technologies.
Requirements
- System Verilog testbench, Verilog/System Verilog logic design/RTL fluency a must
- Pre-existing Experience / familiarity with DDR DRAM technology a strong preference
- Working experience with Python and TCL scripting languages preferred
Responsibilities
- Testbench and test sequence development for verification of new controller technologies and features
- Functional coverage planning, coverage item coding, and test suite augmentation to achieve Functional Coverage
- Regression test development, monitoring, debug/triage, and correction to test environment, sequences, debug of controller RTL design
- Development & support of Verification environment scripting and capabilities
Other
- Bachelors Degree or above in EE/CS, minimum 7 years experience with HDL logic Design-Verification
- Full Time position
- Hybrid work environment
- Competitive compensation package including base salary, bonus, equity, matching 401(k), employee stock purchase plan, comprehensive medical and dental benefits, time-off program, and gym membership.
