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Digital Design Engineer

Meta

$142,000 - $203,000
Aug 17, 2025
Sunnyvale, CA, USA
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Reality Labs (RL) focuses on delivering Meta's vision through Virtual Reality (VR) and Augmented Reality (AR). The compute performance and power efficiency requirements of Virtual and Augmented Reality require custom silicon. Reality Labs Silicon team is driving the state of the art forward with breakthrough work in computer vision, machine learning, mixed reality, graphics, displays, sensors, and new ways to map the human body. Our chips will enable AR & VR devices where our real and virtual world will mix and match throughout the day. We believe the only way to achieve our goals is to look at the entire stack, from transistors, through architecture, firmware, and algorithms.

Requirements

  • Experience in digital design µArchitecture, RTL coding
  • Experience in Machine Learning IPs Silicon development
  • Experience with at least 1 procedural programming language (C, C++, Python etc.)
  • Experience in SoC integration and ASIC architecture
  • Knowledge of Physical Design and Low power implementation
  • Experience with Machine learning models, algorithms or accelerator architecture

Responsibilities

  • Contribute to ASIC digital µArchitecture and design for low-power machine learning hardware accelerator
  • Assist performance/power analysis of the design and help meet the power and performance targets
  • Work with architects to map Machine learning algorithms on the hardware
  • Support hand-off and integration of blocks into larger SOC environments
  • Work across disciplines, brainstorm big ideas, build new methodologies

Other

  • 6+ years of experience as a Hardware Design Engineer for production silicon shipped in volume
  • Individual compensation is determined by skills, qualifications, experience, and location.
  • Meta is proud to be an Equal Employment Opportunity employer.
  • Meta is committed to providing reasonable accommodations for qualified individuals with disabilities and disabled veterans in our job application procedures.