Integration and Verification of a future Intel CPU, driving timing convergence for Full-Chip models
Requirements
- Experience with Static Timing Analysis (STA) using PrimeTime
- Experience with Scripting in one or more of the following languages (TCL, Perl, or Python)
- Experience with verification of power crossing ie. VC-static (VC LP), UPF
Responsibilities
- As an FC Design Engineer, you will perform constraints management and STA verification.
- You will also be responsible for coordinating collateral handoffs between the FC Design team and other functions within back-end design such as Clocking, Power Delivery and Partition synthesis/APR.
- You will drive timing closure and provide collateral for SOC drops.
Other
- Excellent written and oral presentation skills, and willing to work across multiple organizations and geographies.
- Effective team player with continuous learning mindset.
- Strong analytical and problem-solving skills.
- Bachelor's Degree in Electrical Engineering, Computer Engineering or similar field with 4+ years of relevant experience
- Must be willing to work on-site
