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Intel is looking to integrate and verify a future Intel CPU, requiring an engineer with broad Physical Design and Static Timing Analysis skills to drive timing convergence for Full-Chip models and collaborate with multiple functional teams.

Requirements

• Experience with Static Timing Analysis (STA) using PrimeTime
• Experience with Scripting in one or more of the following languages (TCL, Perl, or Python)
• Experience with verification of power crossing ie. VC-static (VC LP), UPF

Responsibilities

• As an FC Design Engineer, you will perform constraints management and STA verification.
• You will also be responsible for coordinating collateral handoffs between the FC Design team and other functions within back-end design such as Clocking, Power Delivery and Partition synthesis/APR.
• You will drive timing closure and provide collateral for SOC drops.

Other

• Excellent written and oral presentation skills, and willing to work across multiple organizations and geographies.
• Effective team player with continuous learning mindset.
• Strong analytical and problem-solving skills.
• Be willing to balance multiple tasks.
• Self-starter with a collaborative spirit, comfortable asking for help when needed
• This role will require an on-site presence.