Chip teams today are still using the same archaic workflows from 30 years ago, resulting in lengthy 12-18 month design cycles and the inability to ship custom chips fast enough to keep up with the software pointer. Silimate's chip design copilot is helping chip designers create correct, PPA-optimized RTL code from the onset, and eliminate months from their tapeout schedule. The goal is to enable autonomous spec-to-design.
Requirements
- Python
- Verilog
- Familiar with basic VLSI frontend concepts & tools (SystemVerilog, common EDA methodology)
- Proficient (or fast-to-ramp) on QA/testing methodology (pytest and more)
- Good at writing/shipping high-quality code (Python) quickly
Responsibilities
- Increasing/adding key test coverage for product features, across EDA tools and chip design samples
- Ensuring seamless product experience for Silimate’s 10+ chip/IP customers (unicorns & enterprises)
- Collaborating directly with the founders on key engineering/QA decisions
Other
- US citizen/visa only
- Available for 15-40 hours/week in-person in Mountain View, CA
- Excited about driving product quality for a fast-moving startup
- You want to work at a scrappy startup that sets and meets aggressive goals.
- You enjoy working in-person with others, and are able to come to our Mountain View office multiple times a week.
