Marvell is looking to develop advanced and highly complex SoCs, from architecture and design all the way through layout, packaging, prototype validation and production ramp up, and the Emulation Center of Excellence (CoE) team is key part of this group, with global ownership and responsibility for delivering emulation infrastructure, validating the design on emulation and drive left shift of software and post-silicon readiness for all of CCS products.
Requirements
- Good understanding of digital logic design using Verilog/System Verilog.
- Knowledge of UVM validation flow or other validation methodologies is a plus.
- Knowledge of simulation tools from any vendors (Cadence, Siemens or Synopsys) is a plus.
- Knowledge of Emulation tools from any vendors (Cadence, Siemens or Synopsys) is a plus.
- Experience in programming and scripting languages such as Python, Perl, Tcl
- Good understanding of Linux/Unix, with experience working on distributed systems
Responsibilities
- Develop understanding of the UVM testbench methodology.
- Build and run a simulation of a Marvell IP using the UVM test methodology
- Understand key concept of the UVM methodology: Agent, Driver, Sequencer, Monitor, Scoreboard
- Review the testbench and understand the part of UVM sequence that would be require in emulation
- Build and run an emulation model using the output of the Python script
- Validate that simulation and emulation behavior are matching
Other
- Currently pursuing a Bachelor's degree in Computer Science, Electrical Engineering, or related fields.
- Effective teamwork and communication skills
- Must be eligible to access export-controlled information as defined under applicable law.
- Except for U.S. citizens, lawful permanent residents, or protected individuals as defined by 8 U.S.C. 1324b(a)(3), all applicants may be subject to an export license review process prior to employment.
