Shape the future of AI/ML hardware acceleration and drive cutting-edge TPU technology that powers Google's most demanding AI/ML applications.
Requirements
- Experience in computer architecture performance analysis
- Experience in developing software systems in C++ or Python.
- Experience in applying computer architecture principles to solve open-ended problems.
- Experience in analyzing workload performance and creating benchmarks.
- Experience in hardware and software co-design.
- Experience developing in Python.
- Knowledge of design of digital logic at the Register Transfer Level (RTL) using Verilog.
- Knowledge of processor design or accelerator designs and mapping Machine Learning (ML) models to hardware architectures.
Responsibilities
- Lead Machine Learning workload characterization, benchmarking, and hardware-software co-design.
- Conduct performance and power analyses and quantitatively evaluate proposals.
- Develop architectural and micro architectural models to enable quantitative analysis.
- Collaborate with partners in hardware design, software, compiler, Machine Learning (ML) model and research teams for hardware/software codesign.
- Propose capabilities and next-generation TPUs and chip roadmap, and contribute to TPU chip specs.
- Model, analyze, and define next-generation TPUs.
- Verify complex digital designs, with a specific focus on TPU architecture and its integration within AI/ML-driven systems.
Other
- Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, a related field, or equivalent practical experience.
- 3 years of experience in computer architecture performance analysis, or a PhD degree in lieu of industry experience.
