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HBM IO Architecture – Principal Engineer

Micron Technology

Salary not specified
Aug 20, 2025
Richardson, TX, USA
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Micron Technology is looking for an HBM IO Design engineer to architecture design and be responsible for the development of the PHY on the interface die in next-generation HBM products. The goal is to deliver the lowest power per bit solutions in the industry for AI and ML applications.

Requirements

  • Good IO circuit design background with familiarity of both, analog and digital design and simulation experience required
  • Good understanding on timing/area/power/complexity tradeoffs on sophisticated interface design
  • Good understanding on FinFET device characteristics and hands-on design experience
  • Familiar with one or more off-chip protocols such as HBM, UCIe or other DRAM
  • Experience with circuit verification and optimization including layout verification and parasitic extractions of the circuits
  • Familiar with IP level verification and strong RTL debugging capabilities is a plus
  • Handy scripting languages, including Python, Tcl, Perl, ACE, and shell is a plus

Responsibilities

  • Pathfinding to explore new IO architectures for future HBM products and make recommendations after performing highly technical feasibility analyses
  • Develop the HBM PHY circuits for the interface die based on industry specifications and working with internal and external partners to consider signal integrity, layout optimization, and ensure closure of timing budgets
  • Work with Product Engineering to correlate silicon measurements and simulation performance for circuit level design analysis
  • Work with HBM memory and interface design teams to ensure HBM product meet industry leading speed, power, cost, and quality metrics
  • Maintain technical expertise and provide training
  • Contribute to cross group communication to work towards standardization and group success
  • Proactively solicit mentorship from Standards, CAD, modeling, and verification groups to ensure the design quality

Other

  • BSEE with 5+ years of proven experience.
  • 5+ years of technical expertise with IO interfaces, including Single-ended Rx, Buffers, IO, Tx, SerDes, Equalizer, DCC, Phase interpolator, etc
  • Excellent problem-solving and analytical skills
  • Strong communication skills with the ability to convey sophisticated technical concepts to other design peers both verbally and written