Rambus is seeking to hire an exceptional RTL Digital Intern to join our Memory Interface Chips team to develop products that make data faster and safer
Requirements
- Background in Digital RTL design including standard LEC, CDC, Lint, DFT, BIST, STA tools
- High aptitude with Verilog and SystemVerilog
- Ability to document design techniques, test, and verification methodology
- Python/perl script development
- Interface with debug, test, product, and reliability engineers for product qualification
- Coursework: Digital Integrated Circuits, Advanced VLSI Systems, Advanced Computer Architecture, Embedded Systems, Design and Analysis of Algorithms, Fundamentals of Machine Learning
Responsibilities
- Develop system Verilog RTL IP, logic, and state machines for next generation products
- Perform full chip integration and chip level simulations
- Estimate and track power, performance, area (PPA) tradeoffs for RTL designs
- Review and improve Static Timing Analysis (STA) results
- Creating Verilog functional models to be used in simulations
- Work closely with verification team
Other
- BS or MS in Electrical Engineering or Computer Engineering
- Ability to work in a hybrid environment with an average of at least three days per week working onsite
- Must be eligible to work in the US
- Rambus is committed to providing reasonable accommodations for qualified individuals with disabilities and disabled veterans during our job application procedures
- Rambus is an Equal Employment Opportunity and Affirmative Action employer
