Rambus is seeking to hire a Digital Verification Intern to develop products that make data faster and safer, specifically working on DDR memory interface products
Requirements
- High aptitude with Verilog and SystemVerilog
- Advanced verification methodologies such as UVM
- Python/perl scripting
- Familiarity with creating constrained-random stimulus and coverage based auto-checking verification environments
- Coursework: Digital Integrated Circuits, Advanced VLSI Systems, Advanced Computer Architecture, Embedded Systems, Design and Analysis of Algorithms, Fundamentals of Machine Learning, Object Oriented Programming
Responsibilities
- Create digital verification plans using datasheets, inputs from engineers/customers, and working closely with system and design engineers
- Implement digital test-benches in SystemVerilog and UVM to apply constrained random stimulus and checks
- Implement Systemverilog Assertions (SVA) to check digital DUT behavior
- Track bugs, functional coverage, and RTL code coverage
- Work with design and systems teams to close bugs as they arise
Other
- BS or MS in Electrical Engineering or Computer Engineering
- Average of at least three days per week working onsite, allowing for two days of remote work
- Competitive compensation package including base salary, bonus, equity, matching 401(k), employee stock purchase plan, comprehensive medical and dental benefits, time-off program, and gym membership
- Rambus is committed to providing reasonable accommodations for qualified individuals with disabilities and disabled veterans during our job application procedures
- Rambus is an Equal Employment Opportunity and Affirmative Action employer
