ASML US is looking to develop and optimize FPGA-based acceleration solutions for AI workloads, specifically for deploying deep learning models on FPGA/SOC platforms to enable high-performance inference for image processing and defect detection applications.
Requirements
- Proficiency in VHDL/Verilog for FPGA development.
- Familiarity with Intel or Xilinx FPGA platforms and AI toolchains (Vitis AI, OpenVINO).
- Understanding of deep learning models (ResNet, YOLO) and image processing techniques.
- Programming skills in C/C++ and Python.
- Coursework or project experience in FPGA design, digital logic, and machine learning.
- Prior exposure to deep learning frameworks (PyTorch/TensorFlow) and hardware acceleration is a plus.
Responsibilities
- Assist in RTL design (VHDL/Verilog), synthesis, timing analysis, and resource optimization on Intel or Xilinx platforms.
- Port and optimize deep learning models (ResNet, YOLO) for FPGA, including quantization, pruning, and hardware mapping using toolchains like Xilinx Vitis AI or Intel OpenVINO.
- Support algorithm development for defect detection and object recognition; prepare datasets and train models using PyTorch/TensorFlow.
- Explore advanced topics such as low-power design, edge AI, and real-time inference; contribute to technical documentation and reports.
- Work closely with hardware and algorithm engineers, participate in technical discussions, and maintain clear documentation.
Other
- Currently pursuing a Bachelor’s or Master’s degree in Electrical Engineering, Computer Engineering, Computer Science, or related fields.
- Ability to analyze performance bottlenecks and optimize hardware resources.
- Strong problem-solving ability, attention to detail, and willingness to learn.
- Good communication and teamwork skills.
- This position is located on-site in San Jose, CA. It requires onsite presence to attend in-person work-related events, trainings and meetings and to further ensure teamwork, collaboration and innovation.
