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Low-Power Design Engineer, ML Accelerators

Google

$183,000 - $271,000
Oct 6, 2025
Sunnyvale, CA, US
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Google is looking to improve the power efficiency of their TPUs (Tensor Processing Units) which power demanding AI/ML applications, by developing custom silicon solutions and optimizing chip power.

Requirements

  • Experience with RTL design using SystemVerilog, Verilog, or similar HDL.
  • Experience with power analysis, sign-off, or management.
  • Experience with low-power design methodologies or applying power reduction techniques.
  • Experience defining and implementing chip-wide power management architectures and designs.
  • Expertise in power modeling, measurement, and correlation across the pre- and post-silicon phases.
  • Understanding of modern power and thermal management techniques at both the silicon and system levels (including DVFS, Turboing, Thermal Management, and system-level tradeoffs).
  • Ability to solve complex, open-ended power and performance problems under ambiguity.

Responsibilities

  • Define best practices and methodologies to achieve low-power RTL designs.
  • Investigate, specify, and deploy architectural and microarchitectural power optimization techniques.
  • Collaborate with cross-functional software and system teams to create novel power management architectures.
  • Contribute to design power modeling and drive convergence to power goals.
  • Drive power efficiency for our TPU designs, starting from building robust power models to proposing novel power optimization techniques.
  • Utilize background in modeling and optimizing chip power, as well as have an understanding of system level power considerations and tradeoffs.
  • Leverage your design and verification expertise to verify complex digital designs, with a specific focus on TPU architecture and its integration within AI/ML-driven systems.

Other

  • 8 years of experience in silicon design, verification, physical design, or post-silicon validation.
  • 10 years of experience in silicon design, verification, physical design, or post-silicon validation.
  • The US base salary range for this full-time position is $183,000-$271,000 + bonus + equity + benefits.
  • Google is proud to be an equal opportunity workplace and is an affirmative action employer.
  • We are committed to equal employment opportunity regardless of race, color, ancestry, religion, sex, national origin, sexual orientation, age, citizenship, marital status, disability, gender identity or Veteran status.