Marvell's Central Engineering Memory Development team designs and implements cutting-edge memory solutions for state-of-the-art ASICs and business units within Marvell, working in advanced process technologies to lead in chip design.
Requirements
- Schematic entry (Cadence Virtuoso), Circuit Simulation (Spectre, MDL), Verification (Verilog, VHDL)
- Statistical analysis of complex circuits across a wide Process, Voltage and Temperature range
- Process and visualize data using scripting tools (Perl, Python, Copilot)
- Verilog test pattern generation, simulation and waveform debug for large, complex memory designs
- Familiarity working in a Unix/Linux environment
- Understanding of analog or digital memory circuits
- Strong Programming Skills in common scripting languages
- Previous exposure to Cadence design tools
Responsibilities
- Design and implement custom digital circuitsoptimizingPower, Performance, and Area metrics (PPA)
- Schematic entry (Cadence Virtuoso), Circuit Simulation (Spectre, MDL), Verification (Verilog, VHDL)
- Statistical analysis of complex circuits across a wide Process, Voltage and Temperature range
- Process and visualize data using scripting tools (Perl, Python, Copilot)
- Verilog test pattern generation, simulation and waveform debug for large, complex memory designs
- Analyze, summarize, document, and present results to stakeholders to justify design approaches
Other
- Candidate MUST be currently pursuing a BS degree in Electrical Engineering or related technical field(s)
- 0-1 years of previous experience
- Ability to work independently with regular check-insand team support
- Strong verbal and written communication skills
- This position may require access to technology and/or software subject to U.S. export control laws and regulations, including the Export Administration Regulations (EAR). As such, applicants must be eligible to access export-controlled information as defined under applicable law.
