Marvell is looking to design and implement cutting-edge memory solutions for state-of-the-art ASICs and business units within Marvell, focusing on custom SRAM compilers, hardware security IP, and software for SoC memory usage in advanced semiconductor nodes.
Requirements
- Candidate MUST be currently pursuing a BS/MS degree in Electrical Engineering or related technical field(s)
- 0-1 years of previous experience
- Pursuing an MS in EE
- Familiarity working in a Unix/Linux environment
- Understanding of analog or digital memory circuits
- Strong Programming Skills in common scripting languages
- Previous exposure to Cadence design tools
Responsibilities
- Design and implement custom digital circuitsoptimizingPower, Performance, and Area metrics (PPA)
- Schematic entry (Cadence Virtuoso), Circuit Simulation (Spectre, MDL), Verification (Verilog, VHDL)
- Statistical analysis of complex circuits across a wide Process, Voltage and Temperature range
- Process and visualize data using scripting tools (Perl, Python, Copilot)
- Verilog test pattern generation, simulation and waveform debug for large, complex memory designs
- Analyze, summarize, document, and present results to stakeholders to justify design approaches
Other
- Candidate MUST be currently pursuing a BS/MS degree in Electrical Engineering or related technical field(s)
- Ability to work independently with regular check-ins and team support
- Strong verbal and written communication skills
