Micron Technology is looking to develop and optimize High Bandwidth Memory (HBM) solutions for AI and ML applications, with the goal of delivering the lowest power per bit solutions in the industry
Requirements
- Prior industrial experience in high-speed clocking design at 16Gbps+ speed
- Prior experience in system level IO timing budgeting
- Proven knowledge of IO design principles for practical design tradeoffs on speed/area/power/complexity
- Familiar with one or more off-chip protocols such as UCIe, HBM, DDR, PCIe, MIPI, etc
- Good understanding on FinFET device characteristics and hands-on design experience
- Deep understanding of signal integrity, channel characteristics, and ESD design techniques and topologies
Responsibilities
- High-speed IO design architecture for HBM products
- Planning IO development on next generation products, set design target of each IO and IO related block
- Work with Product Engineering to correlate silicon measurements and simulation performance for circuit level design analysis
- Contribute to cross group communication to work towards standardization and group success
- Proactively solicit guidance from Standards, CAD, modeling, and verification groups to ensure the design quality
- Drive innovation into the future Memory generation with dynamic work environment
Other
- MS or PhD in EE
- Minimum 10+ years of proven experience in relevant Engineering or Design Engineering experience
- Strong communication skills with the ability to clearly convey sophisticated technical concepts to other design peers both verbally and written
- Excellent problem-solving and analytical skills
- Prior circuit debug experience through Product Engineering or equivalent preferred
