Marvell's custom ASIC offering specializes in addressing the complex, high-speed, high-performance silicon requirements of next generation data center applications. The Marvell Physical Design team located in our Rochester, MN office has a long history of successful design tapeouts in advanced process nodes. Our team is made up of engineers with a broad depth of static timing analysis and physical design engineering experience. Being a part of our team will give you a chance to work on many different aspects of the chip design process, while working alongside some of the best engineers in the industry. In this unique role, you’ll have the opportunity to work on timing analysis for future designs of our next-generation, high-performance data center chips in a leading-edge CMOS process technology.
Requirements
- Strong understanding of digital logic design and timing concepts (setup/hold, clock skew, etc.).
- Familiarity with Verilog and basic scripting languages (e.g., Python, Tcl, or Perl).
- Coursework or project experience in VLSI design or digital IC design is a plus.
- Exposure to STA tools or timing analysis in academic projects.
- Knowledge of CMOS technology and physical design flow.
Responsibilities
- Assist in performing static timing analysis on digital designs using industry-standard EDA tools (e.g., PrimeTime, Tempus).
- Help develop and validate timing constraints (SDC) for various design blocks.
- Support timing closure efforts by identifying and resolving timing violations.
- Collaborate with RTL, synthesis, and physical design teams to understand timing bottlenecks.
- Contribute to automation scripts and flows to improve STA efficiency and accuracy.
- Document findings and present results to the team.
Other
- Currently pursuing a Bachelor’s degree in Electrical Engineering, Computer Engineering, or a related field.
- Excellent problem-solving and communication skills.
- Passion for learning and working in a fast-paced, collaborative environment.
