Marvell Compute and Custom Solutions needs to develop the architecture for a functional verification environment, including reference models and bus-functional monitors and drivers, to deliver leading-edge, high-performance data processing silicon platforms for AI/Accelerated computing, carrier, and cloud/enterprise markets.
Requirements
- Experience with System Verilog, UVM
- Experience with writing a detailed test plan and building a sophisticated, directed, random-verification environment
- Experience with scripting language such as Python or Perl and EDA Verification tools
- Experience with Object-Oriented Design and implementation
- Good understanding of Linux O.S.
- Good programming skills desired, especially C++ and ARM assembly
- Understanding of networking protocols, a plus
Responsibilities
- Develop the architecture for a functional verification environment, including reference models and bus-functional monitors and drivers
- Contribute to the methodology behind such development
- Writing a verification test plan using random techniques and coverage analysis and working with designers to ensure it is complete
- Developing tests and tuning the environment to achieve coverage goals
- Debugging failures and working with designers to resolve issues
- Verifying boot code and architecting, developing, and maintaining tools to streamline the design of state-of-the-art multi-core SoCs
- Transforming the requirements from the engineering teams into software tools that are both easy to use and scalable within a highly parallel compute environment
Other
- Diligent, detail-oriented, and willing to take initiative and handle assignments with minimal supervision
- Requires the ability to accept and work with differing opinions
- Cannot be a close-minded developer
- Must be able to learn on the fly and work in a fast-paced environment
