Silvus Technologies is seeking to address challenging real-world communication needs through the development of novel signal processing algorithms for MIMO wireless networking products.
Requirements
- Demonstrated experience with fixed point binary arithmetic and digital signal processing designs
- Deep knowledge of RTL design fundamentals using Verilog and System-Verilog
- Proven expertise working with front-end RTL design tools, FPGA synthesis, timing closure, multiple clock-domain and/or high-utilization FPGA designs
- Experience with Xilinx FPGAs, SoCs, and the Vivado IDE
- Basic MATLAB skills
- Solid knowledge and understanding of scripting languages such as Perl and Python
- Experience with wireless communication systems on FPGA or ASIC designs
Responsibilities
- Working with system engineers and digital design architecting for wireless communication projects, including fixed point design of signal processing blocks
- RTL coding, simulation, and test bench development
- FPGA synthesis and timing closure
- Hardware verification and troubleshooting; familiarity with logic analyzers
- Provide support to the RF and Software Engineering Teams
Other
- Bachelor of Science degree in Electrical Engineering, Computer Science, or relevant fields
- Minimum 10 years of demonstrated experience in RTL design and FPGA implementation; 8 years of experience in RTL design and FPGA implementation with an advanced degree (MS or PhD) in Electrical Engineering, Computer Science, or relevant fields
- Must be a U.S. Citizen due to clients under U.S. government contracts
- Strong communication and presentation skills
- U.S. Person (permanent resident or citizen) for some Engineering or R&D roles
- Background check clearance
