At Cadence, the business problem is to improve the debuggability, performance, and scalability of multi-billion-gate UPF (Unified Power Format) designs across modular compilation flows (2-state and 4-state) for the Palladium and Protium emulation platforms.
Requirements
- Strong proficiency in object-oriented design and C++ development.
- Experience with standard C/C++ libraries and the C++ STL.
- Demonstrated ability to build high-performance software for large-scale data processing.
- Scripting experience in Perl, Tcl/Tk, and/or Python.
- Familiarity with IEEE 1801 and UPF implementation.
- Experience with Verilog, SystemVerilog, and VHDL.
Responsibilities
- Design, develop, and optimize low-power verification software for Palladium and Protium.
- Improve UPF design debuggability within the IXCOM Modular Compiler and Parallel Partition Compiler (2-state and 4-state).
- Enhance compiled streaming probes and accelerate waveform generation for large-scale designs.
- Collaborate closely with R&D, Product Engineering (PE), and Application Engineering (AE) to deploy UPF solutions across diverse flows, including: AVIP + UPF + 2/4-state, UVMA + UPF + 2/4-state, MC + UPF, Dielets + UPF
- Consolidate and unify UPF software across Palladium and Protium platforms.
- Contribute to major initiatives such as: MC + PPC flow with UPF 4-state, UPF compilation time optimization, Full Vision UPF probe integration, SAGE UPF debug with Verisium
Other
- Bachelor’s degree in Computer Science or Electrical Engineering with 7+ years of relevant experience, OR a Master’s degree with 5+ years, OR a PhD with 1+ year of industry experience.
- Paid vacation and paid holidays
- 401(k) plan with employer match
- Employee stock purchase plan
- A variety of medical, dental and vision plan options
