ByteDance is looking to solve the problem of optimizing its central gateway and host networking components through hardware acceleration technologies, to support its large-scale and highly available cloud and AI networking infrastructure.
Requirements
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- Experience with at least one of the following areas: P4 programming on Tofino switch and/or Pensando DPU
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- Experience with at least one of the following areas: NPL programming on TD4 or TD5
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- Experience with at least one of the following areas: C programming with DPDK
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- Experience with at least one of the following areas: RDMA protocols and AI networking
- -Frequent contributors or maintainers in networking related open source communities.
- -Having top tier networking conference publications such as NSDI or SIGCOMM.
Responsibilities
- -Develop key hardware acceleration technologies to optimize our central gateway & host networking components.
- -Work with academia and open source communities on joint development.
- -Follow the latest technologies from academia and industry and conduct deep-dive analysis.
- -Present our research and products in academic papers.
Other
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- Currently pursuing a PhD in computer networking or a related technical discipline.
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- Commit to proactive continuous learning, demonstrate enthusiasm for networking fields, and exhibit a strong ability to quickly grasp and apply new technologies.
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- Good communication and teamwork skills.
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- Please state your availability clearly in your resume (Start date, End date)
