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Research Scientist Intern, Machine Learning Acceleration (PhD)

Meta

$7,313 - $12,134
Oct 29, 2025
Sunnyvale, CA, United States of America
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Reality Labs (RL) is responsible for delivering Meta’s vision of the next generation of wearable XR systems to enable the next great wave of human-oriented computing. The compute performance and power efficiency requirements of these future XR systems will require the best-in-class custom silicon solutions running the most efficient AI models to enable powerful new AI applications in an all-day wearable form factor.

Requirements

  • Experience with Python and building complex silicon, design automation, or software systems
  • Understanding of agentic workflows and AI tools
  • Understanding of computer architecture, hardware design, and power and performance optimization fundamentals
  • Experience with design, model deployment, and performance optimization of PyTorch models for AI accelerator architectures (e.g. systolic arrays, vector extensions, custom ASICs, etc)
  • Experience applying and integrating AI to accelerate and improve hardware EDA/CAD methodology tool flows
  • Experience in LLM architectures, using LLMs to automate tasks and flows, building agentic workflows, and/or fine-tuning AI models for hardware
  • Experience or familiarity with Tensorflow, Pytorch, MLIR, XLA, JAX, or tensor-rt, and classic ML and CV algorithms like BERT, RNN, CNN, or similar

Responsibilities

  • Collaborate with computer architects, software, ML and silicon researchers and engineers, to map and optimize ML workloads on various backend targets including CPU’s, DSP’s, and Deep Learning Accelerators
  • Perform ML algorithm, software, hardware co-design to achieve best energy and performance efficiency
  • Use AI to build new solutions that aid silicon design with the goal of increasing efficiency and quality of our systems
  • Develop high performance C/C++ kernels and optimize domain specific compilers to port industry standard ML libraries to custom hardware
  • Review SOTA research trends in hardware specific ML model optimizations and mapping
  • Evaluate and integrate promising techniques into shipping products
  • Run analysis/profiling, identify performance and power bottlenecks on the actual hardware, virtual platforms, simulators or emulators and provide feedback for optimizations across the stack

Other

  • Currently has, or is in the process of obtaining, a PhD degree in Computer Science, Computer Engineering, Electrical Engineering, or relevant technical field
  • Must obtain work authorization in the country of employment at the time of hire and maintain ongoing work authorization during employment
  • Intent to return to degree program after the completion of the internship/co-op
  • Experience working and communicating cross functionally in a team environment
  • Proven track record of achieving significant results as demonstrated by grants, fellowships, patents, as well as first-authored publications at leading workshops or conferences such as ISSCC, VLSI, DATE, DAC, ICCAD, ISCA, ASPLOS, MICRO, PLDI, NeurIPs, ICLR, HPCA or similar