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Mem0 Logo

Senior Research Engineer

Mem0

Salary not specified
Oct 27, 2025
San Francisco Bay Area, CA, US
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The company is looking to improve memory features by fine-tuning models for extraction, updates, consolidation/forgetting, and conflict resolution, turning customer pain points into research hypotheses, implementing and benchmarking ideas from papers, and shipping with Engineering to achieve SOTA latency, reliability, and cost. They also aim to build evaluation at scale and close the loop with real-world feedback to continuously improve quality.

Requirements

  • Experience in RAG or information retrieval (retrieval, ranking, query understanding) for real products.
  • Model training/fine-tuning experience (LLMs/encoders) with a strong footing in experimental design and iteration.
  • Strong Python; deep experience with PyTorch and familiarity with vLLM and modern serving frameworks.
  • Built evaluation for complex vision-and-language tasks (gold sets, offline metrics, online tests).
  • Able to orchestrate data pipelines to run these models in production with low-latency SLAs (batch + streaming).
  • Experience with privacy-preserving ML (redaction, differential privacy, data governance).
  • Expertise with embeddings, vector-DB internals, deduplication, and contradiction detection.

Responsibilities

  • Fine-tune and train models for memory extraction, updates, consolidation/forgetting, and conflict resolution; iterate based on data and outcomes.
  • Read, reproduce, and implement research: quickly prototype paper ideas, benchmark against baselines, and productionize what wins.
  • Build evaluation at scale: automated relevance/accuracy/consistency metrics, gold sets, online A/B & interleaving, and clear dashboards.
  • Partner with Engineering to ship: design APIs and data contracts, plan safe rollouts, and maintain SOTA latency, reliability, and cost at scale.
  • Orchestrate data pipelines to run these models in production with low-latency SLAs (batch + streaming).
  • Implement and benchmark ideas from papers.
  • Ship with Engineering to SOTA latency, reliability, and cost.

Other

  • Own the end-to-end lifecycle of memory features—from research to production.
  • Turn customer pain points into research hypotheses.
  • Work closely with customers to uncover pain points, turn them into research hypotheses, and validate solutions through field trials.
  • Clear, concise communication with stakeholders (engineering, product, GTM, and customers).
  • Publications at venues like CVPR, NeurIPS, ICML, ACL, etc.