The modelling team in Arm's Central Engineering Software (CE-SW) division needs to create highly efficient models of Arm Interconnect IP to enable customers to build and validate software on Arm IP-based systems.
Requirements
- Strong understanding of C++ and proven experience developing robust, efficient software, with solid skills in coding, testing, and debugging.
- Good understanding of computer architecture, with the ability to apply concepts such as memory hierarchy, coherency, and interconnect design.
- Experience with programmer’s view modeling, instruction-level simulators (e.g., QEMU, Simics, Gem5, Virtualizer), or SoC virtual prototyping using C/C++/SystemC/TLM.
- Experience with low-level or bare-metal software, firmware or device-driver development.
Responsibilities
- Develop, test, and maintain robust, efficient C++ models of Arm’s Interconnect IP for use in system-level simulation.
- Deliver models in iterative increments that meet evolving partner requirements and enable early feedback.
- Collaborate with architects and hardware engineers to understand next-generation hardware designs while they are still in development.
- Work with CE-SW engineers to integrate software on Arm’s Virtual Platform and diagnose issues.
- Foster open idea-sharing and constructive challenge within the team to drive better technical and collaborative outcomes.
Other
- Strong communication and collaboration skills to build consensus, share knowledge, and further a constructive team culture.
- Bachelor's, Master's, or Ph.D. degree in a relevant field (not explicitly mentioned but implied)
- Ability to work in a hybrid environment with flexibility to split time between the office and other locations
- Must be eligible to work in the United States (not explicitly mentioned but implied)
- Accommodations and adjustments available during the recruitment process, including breaks between interviews, having documents read aloud, or office accessibility
