Marvell is looking to solve the problem of delivering high bandwidth over long distances by performing analog validations on amplifiers that drive optical electronic devices and receivers, validating silicon photonics, doing upper electronic measurements, and supporting the coherent digital signal programming unit.
Requirements
- Strong understanding of high-speed SERDES, equalization technique and PCIe protocols.
- 3-10 years experience with High Speed IO testing, debugging and validation.
- Strong lab skills with hands on experience, in system bring up, system testing and debug.
- In-depth working knowledge of test equipment used for SERDES characterization (Scope, BERT, Network analyzer, etc.).
- Working knowledge of PCIe interface and characterization.
- Extensive knowledge of the physical and protocol levels (PIPE I/F, PCS, MAC) of one or more common high-speed interfaces is an asset.
- Working experience with Perl or Python.
Responsibilities
- Complete responsibility of PCIe PHY Validation in post-silicon environment.
- Defining, documenting, executing, and reporting the overall PHY validation/test plan for Marvell storage devices.
- Lab-based silicon bring-up and unit test execution focused on PCIe Physical and PCS layer hardware and firmware functionality, while also extending to the protocol layer of the PCIe stack.
- Perform high speed signal validation and analysis using various test equipment to measure Eye diagram/Jitter/BER.
- Analyze and debug issues on PHY protocol of storage interface (SATA, SAS, PCIe, Ethernet).
- Troubleshoot failing tests with diagnostics, software tools, hardware analyzers, oscilloscopes, meters, logic/protocol analyzers.
- Leading collaborative technical discussions to drive resolution on technical issues.
Other
- Bachelor’s degree in Computer Science, Electrical Engineering or related fields and 5-10 years of related professional experience.
- Master’s degree and/or PhD in Computer Science, Electrical Engineering or related fields with 3-5 years of experience.
- Strong analytical, problem-solving and communication skills.
- Work with cross-functional teams and external vendors to debug any post-silicon and/or customer issues related to PCIe PHY.
- Work closely with customers to address design issue and debug failure cases.
