At AMD, the business problem is to build great products that accelerate next-generation computing experiences, and the role of a Design-for-Testability (DFT) Engineer is to ensure robust and efficient test solutions to solve this problem.
Requirements
- Strong understanding of Design For Test methodologies and DFT verification (e.g., IEEE1500, JTAG 1149.x, scan, memory BIST).
- Experience with Tessent TestKompress and Silicon Scan Network (SSN).
- Proficiency with VCS simulation tools, Perl/Shell scripting, and Verilog RTL design.
- Exposure to static timing analysis and timing closure processes.
- Experience in pre-silicon test planning, validation, and engagement with design teams.
- Skilled in characterization and debugging of scan/ATPG tests in new silicon designs and process technologies.
- Expertise in optimizing test flows for quality enhancement and cost reduction.
Responsibilities
- Implement and verify DFT and Design-for-Debug (DFD) architectures and features.
- Insert Scan, JTAG, and Boundary Scan chains; generate ATPG patterns.
- Generate, implement, and verify Memory Built-In Self-Test (BIST) logic.
- Apply low power DFT techniques to designs.
- Achieve DFT timing closure and verify ATPG patterns through gate-level simulation with timing.
- Analyze test coverage and work on reducing test costs.
- Provide post-silicon support to ensure successful bring-up and improve yield learning.
Other
- Bachelor’s or Master’s degree in Computer Engineering, Electrical Engineering, or a related field.
- Excellent communication skills and ability to work effectively in a global team environment.
- Ability to analyze part failures to improve test coverage and yield.
- Ability to work in a collaborative team environment and take ownership of tasks through to completion.
- Ability to communicate effectively both verbally and in writing.
