Siemens Industry Software Inc. is looking to develop comprehensive verification IPs for interfaces such as PCIe Gen5/Gen6, USB3.2, 400Gigabit Ethernet, DDR5, LPDDR5 and leading coherency protocols like CXL for use with Questa RTL simulation
Requirements
- Good level of SV, UVM Working experience
- Fair level of experience on Assertions, Coverage, Test Plan, BFM design, debug, loggers and trackers
- Understanding of one or more standard bus protocols, like PCIe/CXL, USB, Ethernet, Memory, CHI etc.
- Working of coherent/non-coherent NOC would be an added advantage
- Understanding of latency, bandwidth and performance at system level
- 15+ years of working experience in RTL design, IP/VIP development/verification or emulation experience with industry leadership
- B.Tech/M.Tech in Electronics or related field from reputed institute
Responsibilities
- Developing comprehensive verification IPs for interfaces such as PCIe Gen5/Gen6, USB3.2, 400Gigabit Ethernet, DDR5, LPDDR5 and leading coherency protocols like CXL for use with Questa RTL simulation
- Working with filed (PEs and AEs) or directly interacting with customers to deploy/resolve customer issues
- Implementation means trying, testing, and improving outcomes until a final solution emerges
- Knowledge means exchange discussions with colleagues from all over the world
- Working on C/SystemC based tests
- Understanding of Register layering
- Understanding various components like CPU, GPU, Display, Network, Device, Memory
Other
- B.Tech/M.Tech in Electronics or related field from reputed institute
- 15+ years of working experience in RTL design, IP/VIP development/verification or emulation experience with industry leadership
- Travel may be required
- Equal Employment Opportunity Employer
- Reasonable Accommodations available
