Annapurna Labs (AWS UC) is seeking to design silicon and software that accelerates innovation, specifically for the next generation of ML ASIC, and needs a Senior Substrate CAD layout Engineer to participate in the definition and implementation of substrate and PCB boards.
Requirements
- 7+ years of experience of PCB layout design
- 7+ years of current experience using Cadence Allegro PCB Design/CIS
- 7+ years of current experience using Cadence SIP and APD
- 7+ years of experience with high speed and impedance circuits
- 7+ years of experience with compact, dual side assembly design
- Experience with HDI design
- Experience with BGA pitch of equal or less than 0.5mm
Responsibilities
- Work with the Electrical Engineering hardware team to provide PCB board design services
- Work with fabrication vendors to supply data and seek fabrication design requirements
- Work with assembly vendors to supply data and seek assembly design requirements
- Deliver best in class Substrate/PCB design to high-volume manufacturing
- Assist as necessary in schematic and PCB footprint development
- Work with the company PLM system to write and release ECO’s
Other
- B.S. in Electrical Engineering or related field
- Ability to collaborate and communicate with all cross functional teams and external customers
- Ability to reduce risk of fabrication/assembly/test with a thorough knowledge in each area and taking preventative action early in the design phase
- M.S. in Electrical Engineering or related field (preferred)
- 15+ years’ experience of PCB layout design (preferred)
