Marvell's semiconductor solutions are the essential building blocks of the data infrastructure that connects our world. Across enterprise, cloud and AI, automotive, and carrier architectures, our innovative technology is enabling new possibilities. ASIC design engineer responsible for planning and coordinating the design, verification, and evaluation of digital circuits in high-speed data communication ICs.
Requirements
- Fundamental concepts in digital design, design verification, and timing closure (STA) in support of high-speed analog mixed-signal SerDes design
- Concepts in physical and layout design
- Verilog coding
- Experience with design flow and methodology
- Experience with silicon validation support
- Experience with power analysis and optimization
- Strong Perl and Tcl scripting skill
Responsibilities
- Collaborate with Analog/DSP/DV/FW/AE teams to coordinate the delivery of competitive SerDes IP solutions for all the Marvell product lines
- Understand and improve the unique in-house design methodology and flow
- Provide support to the product teams for both pre and post silicon
- Lead the development and execution of RTL designs for various type of SerDes IPs ranging from 10Gbps to 224Gbps data-rates for different applications
- Work with cross-functional teams to define requirements, create schedules and budgets, manage risks, and communicate with stakeholders
- Identify and mitigate risks to project success
- Track and report on analog mixed-signal IP development progress
Other
- Bachelor degree in Computer Science, Electrical Engineering or related fields and 5-10 years of related professional experience
- Master degree and/or PhD in Computer Science, Electrical Engineering or related fields with 1-3 years of experience
- Good personal communication skills and collaborative spirit
- Strong work ethic and motivation to be part of a highly competent design team
- Excellent cross-discipline communication and interpersonal skills
