Design an edge accelerator for GenAI, based on https://dl.acm.org/doi/full/10.1145/3768168
Requirements
- RTL design
- Embedded DRAM options
- 3D memory array evaluations
- Generative AI workloads
- Accelerator latency and energy evaluations
- Embedded NVM options and evaluations
Responsibilities
- Design an edge accelerator for GenAI, based on https://dl.acm.org/doi/full/10.1145/3768168
- Evaluate PPA by RTL at N7 for all necessary building blocks
- Evaluate and benchmark different memory options, including various eDRAM and eNVM
- Evaluate various 3D array design options by considering the integration scheme (bonding, monolithic, hybrid) and granularity of 3D connections
- Analyze the viability of the low-power memory access schemes at extreme bandwidth proposed in the reference and offer solutions tailored for specific memory devices and arrays
- Quantify the differences between the new design and the analytical estimation in the reference
- Include workload-level energy and latency benchmarks for the considered technology options
Other
- Ph.D. Student in Electrical Engineering or Computer Science
- Summer 2026
- The Company supports a thriving ecosystem of global customers and partners with the industry’s leading process technologies and a portfolio of design enablement solutions to unleash innovation for the global semiconductor industry.
- With global operations spanning Asia, Europe, and North America, TSMC serves as a committed corporate citizen around the world.
- In North America, TSMC has a strong sales and service organization that works with customers by helping them achieve silicon success with cutting-edge technologies and manufacturing excellence.
