AMD is looking to define next generation on the architecture, development, and validation of commercial and radiation tolerant FPGA/ACAP solutions, for the Terrestrial (Telecom, Avionics, Automotive, Datacenter, AI, etc.) and Space markets.
Requirements
- Basic Device Physics, Electrical Engineering skills,
- RAS, HW development, basic SW Coding skills (python, etc.),
Responsibilities
- Assist with roadmap activities for 7nm Versal devices, including development of test benches, accelerated beam testing, and data analysis for current terrestrial and space solutions.
- Support the Next-Generation Architecture definition for Single Event Effects (SEE) and Reliability, Availability, and Serviceability (RAS).
Other
- US citizen or Permanent Resident
- Student enrolled in a Masters or PhD in electrical or computer engineering or an allied field with some focus on FPGA architecture or algorithms
- Onsite/Hybrid: These roles require the student to work full time (40 hours a week) onsite throughout the duration of the co-op/intern term.
- Summer: May 18, 2026 - August 7, 2026 or June 22, 2026 – September 11, 2026
